Date of Award

2008

Degree Type

Thesis Project

Degree Name

Master of Engineering (MEng)

Department

Electrical and Computer Engineering

First Advisor

Andy G. Ye

Abstract

Since the introduction of DSP blocks in commercial FPGAs such as Altera Stratix II and Xilinx Virtex II, DSP applications are increasingly being implemented on FPGAs. This project implements a pipelined difital FIR filter with programmable coefficient in an Altera Cyclone II FPGA. An automated test system is also constructed to verify the design. The project places equal emphasis on implementing a programmable FIR as well as building an automated test system. Also, we will evaluate the pracicality of the design by comparing the design to the FIR IP core provided by Altera.