Date of Award
Master of Applied Science (MASc)
Electrical and Computer Engineering
In the presented work the FPGA based run-time reconfigurable platform with temporal partitioning of hardware resources is proposed. This platform is based on the Field Programmable Gate Array (FPGA) device that can be reconfigured "on-fly" to provide the optimal adaptation of a processing architecture to the algorithm and data structure by utilization of developed mechanisms of temporal partitioning of computational / logic resources. It was shown that the proposed approach allows reaching very high cost-effectiveness of the computing platform oriented on processing of framed data-streams. On the other hand, the hardware programming and compilation processes could be simplified by utilization of library of precompiled Virtual Hardware Components stored in the on-board FLASH memory. Paper presents theoretical proof of the proposed approach by analytical comparison of the performance that could be reached on the conventional processors and FPGA platform with Temporal Partitioning Mechanism (TPM) of hardware resources. The implementation of the proposed TPM on the basis of Xilinx Spartan-3 and Xilinx Virtex II FPGA devices is described. Experimental results gained on the prototype of the FPGA based platform with TPM are discussed and analyzed. Keywords: reconfigurable computing, data-stream processing, FPGA, run-time reconfiguration, temporal partitioning.
Kirischian, Valeri, "FPGA based computing platform with temporal partitioning mechanism" (2005). Theses and dissertations. Paper 385.