A 0.8 V folded cascode operational amplifier was designed in 0.18 μm standard CMOS technology. Emphasis was placed on observing the low voltage design and using a current driven bulk (CDB) technique to achieve this goal. The CDB technique was introduced as a method for low voltage design by reducing the threshold voltage. This design achieves 141 dB DC gain, 56 MHz 3 dB bandwidth and 65 GHz gain bandwidth, which is the working condition of pipeline ADCs.
Ardalan, S; Raahemifar, K; and Yuan, Fei, "Low voltage cascode amplifier" (2002). Electrical and Computer Engineering Publications and Research. Paper 10.